; ioports.i -- definitions of ISUAL DPU I/O ports ; ; 19 FEB 2002 ; CAI ; Revised 20 March 2002 ; SPG ; ; _O = output port, _I = input port ; ; Ports 00-7Fh are in the ISDPGLU Actel: ; SOFTWARE_RESET_O EQU 00h ; forces hardware reset INTVECTOR_STS_I EQU 00h ; C7, CF, D7, ... , FF IRQ_ENABLE_O EQU 01h ; set RST[7:2] interrupt request enables IRQ_ENABLE_I EQU 01h ; read RST[7:2] interrupt request enables BANK_SELECT_O EQU 02h ; memory bank select for CPU addr 4000-7FFF BANK_SELECT_I EQU 02h ; memory bank select for CPU addr 4000-7FFF WATCHDOG_PET_O EQU 03h ; pet watchdog timer, data =xx WATCHDOG_STS_I EQU 03h ; [7:4]=bites, [3:0]=barks CMD_RX_I EQU 04h ; command UART rx data SOH_TX_O EQU 04h ; SOH UART tx data CMD_SOH_CTRL_O EQU 05h ; CMD/SOH UART control CMD_SOH_STS_I EQU 05h ; CMD/SOH UART status PROM_ENBL_O EQU 06h ; PROM enable STATUS6_I EQU 06h ; PROM/reset/CDI/HKP/PS16 status IRQ_LEVELS_I EQU 07h ; RST[7:2] raw levels ; MM_IM_DCM_CTL_O EQU 08h ; MM/Imager/DCM control MM_IM_DCM_STS_I EQU 08h ; MM/Imager/DCM status IDC_RESET_I EQU 09h ; IDC Reset IDC_RESET_O EQU 09h ; IDC Reset ; (0Ah-0Bh not used) RES_FLAG_CLR_O EQU 0Ch ; clear SWR, POR flags ONE_HZ_CLR_O EQU 0Dh ; clear 1-Hz IRQ latch TIMER_SET_L_O EQU 0Eh ; 1024-Hz countdown timer low byte TIMER_SET_H_O EQU 0Fh ; 1024-Hz countdown timer high byte ; ; (10h-3Fh not used) ; CDI_DAT_LO_O EQU 40h ; CDI data low byte CDI_DAT_HI_O EQU 41h ; CDI data high byte CDI_CMD_O EQU 42h ; CDI readback command (write last) CDI_DAT_LO_I EQU 40h ; CDI readback low byte CDI_DAT_HI_I EQU 41h ; CDI readback high byte PWR_STS_LO_I EQU 42h ; power service [7:0] status PWR_STS_HI_I EQU 43h ; power service [15:8] status ; (44h-5Fh not used) ; MM_BADR_0700_O EQU 60h ; mass mem block base address [7:0] MM_BADR_1508_O EQU 61h ; mass mem block base address [15:8] MM_BADR_2316_O EQU 62h ; mass mem block base address [23:16] MM_BADR_3124_O EQU 63h ; mass mem block base address [31:24] MM_WADR_0700_I EQU 60h ; mass mem working address [7:0] MM_WADR_1508_I EQU 61h ; mass mem working address [15:8] MM_WADR_2316_I EQU 62h ; mass mem working address [23:16] MM_WADR_3124_I EQU 63h ; mass mem working address [31:24] ; (64h-6Fh not used) ; SC_TIME_0_O EQU 70h ; set S/C time 2^-16 seconds (write 1st) SC_TIME_1_O EQU 71h ; set S/C time 2^-8 seconds SC_TIME_2_O EQU 72h ; set S/C time 2^0 seconds SC_TIME_3_O EQU 73h ; set S/C time 2^8 seconds SC_TIME_4_O EQU 74h ; set S/C time 2^16 seconds SC_TIME_5_O EQU 75h ; set S/C time 2^24 seconds (write last) ; SC_TIME_0_I EQU 70h ; read S/C time 2^-16 seconds (read 1st) SC_TIME_1_I EQU 71h ; read S/C time 2^-8 seconds SC_TIME_2_I EQU 72h ; read S/C time 2^0 seconds SC_TIME_3_I EQU 73h ; read S/C time 2^8 seconds SC_TIME_4_I EQU 74h ; read S/C time 2^16 seconds SC_TIME_5_I EQU 75h ; read S/C time 2^24 seconds (read last) ; SCIF_CTL_O EQU 76h ; S/C I/F control (NOM/RED, PPS) SCIF_STS_I EQU 76h ; S/C I/F status (NOM/RED, PPS, SCT fault) ISDPGLU_REV_I EQU 77h ; ISDPGLU Actel revision ; (78h-7Fh not used) ; ; Ports 80-BFh are in the ISDPPWR Actel: ; ISDPPWR_REV_I EQU 80h ; ISDPPWR Actel revision FW_STS_I EQU 81h ; filter wheel position status FW_CNTR_O EQU 82h ; set filter wheel counter (N-1 @ 1280 Hz) FW_CNTR_I EQU 83h ; read filter wheel counter (N-1 @ 1280 Hz) FW_CTL_O EQU 83h ; filter wheel & stepper motor control FW_CTL_I EQU 83h ; filter wheel & stepper motor status HKP_DAT_0_I EQU 84h ; 1st housekeeping byte from power controller HKP_DAT_1_I EQU 85h ; 2nd housekeeping byte from power controller HKP_DAT_2_I EQU 86h ; 3rd housekeeping byte from power controller HKP_DAT_3_I EQU 87h ; 4th housekeeping byte from power controller AP_PWR_NOM_O EQU 84h ; set AP to nominal power AP_PWR_RED_O EQU 85h ; set AP to redundant power AP_PWR_OFF_O EQU 86h ; set AP +28V power off AP_PWR_ON_O EQU 87h ; set AP +28V power on HKP_CTL_O EQU 88h ; housekeeping transfer control HKP_STS_I EQU 88h ; housekeeping transfer status STIM_CTL_I equ 89h STIM_CTL_O EQU 89h ; Imager, SP stim control HVERR_STS_I equ 8Ah HVERR_CLR_O equ 8Ah ; (unused) equ 8Bh DAY_LAT_STS_I EQU 8Ch ; day sensor latch status DAY_LAT_CLR_O EQU 8Ch ; clear day sensor latches DAY_SENS_CTL_O EQU 8Dh DAY_SENS_STS_I EQU 8Dh ; day sensor raw status DAY1_THR_I equ 8Eh DAY1_THR_O equ 8Eh DAY2_THR_I equ 8Fh DAY2_THR_O equ 8Fh MCP_DAY_I equ 90h MCP_DAY_O equ 90h MCP_NITE_1_I equ 91h MCP_NITE_1_O equ 91h MCP_NITE_2_I equ 92h MCP_NITE_2_O equ 92h MCP_NITE_3_I equ 93h MCP_NITE_3_O equ 93h MCP_NITE_4_I equ 94h MCP_NITE_4_O equ 94h MCP_NITE_5_I equ 95h MCP_NITE_5_O equ 95h MCP_NITE_6_I equ 96h MCP_NITE_6_O equ 96h MCP_NITE_7_I equ 97h MCP_NITE_7_O equ 97h MCP_MAX_I equ 98h MCP_MAX_O equ 98h MCP_DAC_I equ 99h HV_CNTR_I equ 9Ah HV_CNTR_O equ 9Ah HV_STS_I equ 9Bh HV_CTL_O equ 9Bh PHOS_DAY_I equ 9Ch PHOS_DAY_O equ 9Ch PHOS_SPR_AUR_I equ 9Dh PHOS_SPR_AUR_O equ 9Dh PHOS_MAX_I equ 9Eh PHOS_MAX_O equ 9Eh PHOS_DAC_I equ 9Fh SP1_DAY_I equ 0A0h SP1_DAY_O equ 0A0h SP1_SPR_I equ 0A1h SP1_SPR_O equ 0A1h SP1_AUR_I equ 0A2h SP1_AUR_O equ 0A2h SP1_DAC_I equ 0A3h HV_UNLOCK_0_O equ 0A3h SP2_DAY_I equ 0A4h SP2_DAY_O equ 0A4h SP2_SPR_I equ 0A5h SP2_SPR_O equ 0A5h SP2_AUR_I equ 0A6h SP2_AUR_O equ 0A6h SP2_DAC_I equ 0A7h HV_UNLOCK_1_O equ 0A7h SP3_DAY_I equ 0A8h SP3_DAY_O equ 0A8h SP3_SPR_I equ 0A9h SP3_SPR_O equ 0A9h SP3_AUR_I equ 0AAh SP3_AUR_O equ 0AAh SP3_DAC_I equ 0ABh HV_UNLOCK_2_O equ 0ABh SP4_DAY_I equ 0ACh SP4_DAY_O equ 0ACh SP4_SPR_I equ 0ADh SP4_SPR_O equ 0ADh SP4_AUR_I equ 0AEh SP4_AUR_O equ 0AEh SP4_DAC_I equ 0AFh HV_UNLOCK_3_O equ 0AFh SP5_DAY_I equ 0B0h SP5_DAY_O equ 0B0h SP5_SPR_I equ 0B1h SP5_SPR_O equ 0B1h SP5_AUR_I equ 0B2h SP5_AUR_O equ 0B2h SP5_DAC_I equ 0B3h SP6_DAY_I equ 0B4h SP6_DAY_O equ 0B4h SP6_SPR_I equ 0B5h SP6_SPR_O equ 0B5h SP6_AUR_I equ 0B6h SP6_AUR_O equ 0B6h SP6_DAC_I equ 0B7h ; (B8-BF unused) ; Ports C0-DFh are on DPU and not in Actels: ; (0C0h-0DFh not used) ; ; Ports E0-FFh are on DPU Test Pod: ; (0E0h-0E3h not used) DTP_RX_I EQU 0E4h ; debug UART rx data DTP_TX_O EQU 0E4h ; debug UART tx data DTP_CTRL_O EQU 0E5h ; debug UART control DTP_STS_I EQU 0E5h ; debug UART status DTP_SENSE_I EQU 0E6H ; debug Sense PB and PROM status DTP_SCOPE_TRG_O EQU 0E6H ; debug scope trigger ; (0E7h-0EFh not used) ; DTP_LCD_CTL_O EQU 0F0H ; LCD control DTP_LCD_DAT_O EQU 0F1H ; LCD write data DTP_LCD_STS_I EQU 0F2h ; LCD status DTP_LCD_DAT_I EQU 0F3h ; LCD read data ; (0F4h-0FFh not used) ; ; ; ; Restart vector addresses ; RST_0 equ 00h RST_1 equ 08h RST_2 equ 10h RST_3 equ 18h RST_4 equ 20h TRAP equ 24h RST_5 equ 28h RST_55 equ 2Ch RST_6 equ 30h RST_65 equ 34h RST_7 equ 38h RST_75 equ 3Ch ; JMP_OPCODE equ 0C3h